Saturday, 28 December 2013


  • 1.      Emitter coupled is the fastest of the logic families
  • 2.      The sequence of the steps for designing HDL is called Design Steps
  • 3.      A Parity Bit is used for the purpose of detecting errors
  • 4.      The addition and subtraction operations can be combined into one circuit with one Common Binary Adder
  • 5.      In Digital Priority Encoder the circuit identifies both the highest priority and second highest priority asserted signal
  • 6.      The information stored in the memory elements at any given time defines the present state of the Sequential Circuits
  • 7.      The basic SR Flip Flop is used with Complement Inputs
  • 8.      The Master Slave combination can be constructed for any type of flip flop
  • 9.      The  counter type is Direct type of ADC
  • 10.  The number of comparators required for n-bit A /D convertors are 2n-1
  • 11.  A decimal-to-BCD encoder will have 10 number of inputs
  • 12.  An encoder is an digital circuit that perform the Inverse Operation of decoder
  • 13.  D-flip flop is said to be transparent
  • 14.  A Bi-directional shift register allows shifting of data either to the left or right
  • 15.  In a master-slave flip flop, the master is enabled when the gate is High


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